Optimizing accelerators for CNN inferencing on FPGAs

With CNNs’ rapidly increasing computational and memory demands, deploying computer vision solutions to the edge is becoming more challenging.  Join us for a webinar on Thursday 12th November to see how Core Deep Learning (CDL) creates tailor made hardware accelerators for inferencing on FPGAs to achieve real-time performance with minimal resource usage.

Hardus Richter of ASIC Design Services will take you through the CDL CNN Accelerator design flow. This flow goes through CNN optimization, automated accelerator design, to the final accelerator block that is implemented in the FPGA.

Case studies will be presented on how design space exploration coupled with a network-aware approach can be used to realize the true performance of the available FPGA resources or to create low power designs that meet specific resource constraints.

This webinar investigates the benefits and drawbacks of a configurable solution, such as CDL, as opposed to widely available overlay architectures, with regards to:

      • Dedicated Accelerator vs General Accelerator
      • High performance accelerator design
      • Low power accelerator design
      • FPGA/ASIC design to meet specific network performance constraints
      • CNN to FPGA Design Flow

Thursday 12th November 2020

Virtual event based on Teams

Optimizing accelerators for CNN inferencing on FPGAs

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    For Europe and Asia:10.00-10.30am (GMT) *11.00-11.30pm (CET) *2.30-3.00pm (IST)For Americas: 10.00-10.30am (PST) *11.00-11.30am (MST) *12.00-12.30pm (CST) *1.00-1.30pm (EST)

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