Deep Learning Training
Deep Learning Training

AI at the edge: Implementing CNN's in low-Power FPGAs

CNNs are typically implemented in GPUs that consume hundreds of Watts, are relatively heavy and often require active cooling.
What if you need less accuracy, but are limited in weight, Power-consumption and PCB real-estate.
We starts with an overview of AI and Deep Learning presented by Doulos, a world renown provider of training solutions for engineers creating electronic products.
We then demonstrate how to implement CNNs in low-Power FPGAs using Microchip’s PolarFire™ FPGAs.  This FPGA technology consumes 50% less Power than comparable SRAM-FPGAs in packages as small as 11 mm x 11 mm.
If you have never designed an FPGA before, we use a very simple example just to demonstrate the design flow.
By attending this workshop you will understanding exactly what steps are involved for implementing CNNs in low-Power FPGAs and how ASIC Design Services and Arrow can help you to speed-up your development process.


09h00 – 09h10 a.m. *Welcome by Arrow
09h10 – 10h10 a.m. *“AI in a nutshell“ by Doulos
10h20 – 11h20 a.m. *Core Deep Learning Development Framework & Demos by ASIC Design Services
11h30 – 12h30 a.m.*Person Presence detection by ASIC Design Services using SMF2000, Laptop Camera & UART to video data to CNN. Hands-On session requiring SMF2000
12h30 – 13h00 a.m.*Wrap Up

*MEST (Middle European Summer Time)

Free of Charge

Requires SMF2000

5th May 2020

Virtual event based on Teams

CDL & Arrow AI on "FPGA Workshop" Recording Registration

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