CNNs are typically implemented in GPUs that consume up to 30 Watts, are relatively heavy and often require active cooling. What if you need less accuracy, but are limited in weight, Power-consumption and PCB-real-estate?
This workshop is demonstrating how to implementing low-Power CNNs in FPGAs. In this workshop we use Microchip’s PolarFire FPGAs that consume 50% less Power than comparable SRAM-FPGAs and provide package sizes as low as 11 mm x 11 mm.
If you never designed with FPGAs before we use a very simple example just to demonstrate the design flow.
You will walk out this course and understand exactly what steps are involved to implementing low-Power CNNs in FPGAs and how ASIC Design Services and Arrow can help you to speed-up your development process.