Core Deep Learning

A deep learning FPGA platform optimized for implementation on FPGAs.

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Overview and Flow

Core Deep Learning (CDL) from ASIC Design Services is a scalable and flexible Convolutional Neural Network (CNN) solution for FPGAs. CDL accelerates a wide range of layers typically associated with CNNs . The configurable nature, small real-estate, and low-power properties of FPGAs allow for computationally expensive CNNs to be moved to the node. CDL is the product of a scalable framework that offers the opportunity to stipulate the desired performance, platform specifications, and resource constraints for an application and platform-specific optimized solution

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Comprehensive Layer Support

Concatenation Layer
Convolution
Pooling
Activation
Fully connected
Batch normalisation

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Scalability

The CDL framework is a scalable and flexible embedded deep learning solution that allows for the implementation of a wide range of convolutional neural networks on FPGAs. Considering the different sources of parallelism, minimizing the memory footprint through data quantization, and exploring the design space allows for an efficient chip specific, network specific implementation of CNNs on a FPGA.

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Network Compression

Dynamic 8-bit fixed point representation
Negligible accuracy loss
Reduced external memory bandwidth requirements

FPGA design

Easy Integration

CDL can fit into any FPGA design by scaling to unique customer requirements. Using search and simulation algorithms, optimal solutions are provided on a per-implementation basis. Each solution is configured specific to the network and user-specific platform requirements. The simple interface allows for fast and efficient design integration.

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Benchmarking

Network	Squeezenet	Squeezenet	Tiny-Yolo v2	Tiny-Yolo v2	VGG16 (SVD)	VGG16 (SVD)
Network GOPs	0.86	0.86	6.97	6.97	30.76	30.76
BRAM usage (Mbits)	11.7	12.07	10.45	12.07	15.45	12.07
DSP usage	258	514	258	514	258	514
FPS	87	134	21	33	5	8
Power (w)	2.85	3.44	2.58	3.25	3.24	3.43