A deep learning platform optimized
for implementation on FPGAs
Core Deep Learning (CDL) from ASIC Design Services is a scalable and flexible Convolutional Neural Network (CNN) solution for FPGAs. CDL accelerates a wide range of layers typically associated with CNNs . The configurable nature, small real-estate, and low-power properties of FPGAs allow for computationally expensive CNNs to be moved to the node. CDL is the product of a scalable framework that offers the opportunity to stipulate the desired performance, platform specifications, and resource constraints for an application and platform-specific optimized solution.
Inference on the Node
Why FPGAs for inference
Core Deep Learning
CDL can fit into any FPGA design by scaling to unique customer requirements. Using search and simulation algorithms, optimal solutions are provided on a per-implementation basis. Each solution is configured specific to the network and user-specific platform requirements. The simple interface allows for fast and efficient design integration.