Core Deep Learning
A deep learning FPGA platform optimized for implementation on FPGAs.
Overview and Flow
Core Deep Learning (CDL) from ASIC Design Services is a scalable and flexible Convolutional Neural Network (CNN) solution for FPGAs. CDL accelerates a wide range of layers typically associated with CNNs . The configurable nature, small real-estate, and low-power properties of FPGAs allow for computationally expensive CNNs to be moved to the node. CDL is the product of a scalable framework that offers the opportunity to stipulate the desired performance, platform specifications, and resource constraints for an application and platform-specific optimized solution
Comprehensive Layer Support
- Concatenation Layer
- Fully connected
- Batch normalisation
The CDL framework is a scalable and flexible embedded deep learning solution that allows for the implementation of a wide range of convolutional neural networks on FPGAs. Considering the different sources of parallelism, minimizing the memory footprint through data quantization, and exploring the design space allows for an efficient chip specific, network specific implementation of CNNs on a FPGA.
- Dynamic 8-bit fixed point representation
- Negligible accuracy loss
- Reduced external memory bandwidth requirements
CDL can fit into any FPGA design by scaling to unique customer requirements. Using search and simulation algorithms, optimal solutions are provided on a per-implementation basis. Each solution is configured specific to the network and user-specific platform requirements. The simple interface allows for fast and efficient design integration.
|Network||Squeezenet||Squeezenet||Tiny-Yolo v2||Tiny-Yolo v2||VGG16 (SVD)||VGG16 (SVD)|
|BRAM usage (Mbits)||11.7||12.07||10.45||12.07||15.45||12.07|
Services and Solutions
We Can Engage on Several Levels
- Feasibility Study Specification
- CNN Model and Training
- CNN Quantization and Fine-tuning
- Core Optimization
- Core Implementation
FPGA CNN solution
EXPERIENCE FOR YOURSELF