A deep learning platform optimized
for implementation on FPGAs
Overview
Core Deep Learning (CDL) from ASIC Design Services is a scalable and flexible Convolutional Neural Network (CNN) solution for FPGAs. CDL accelerates a wide range of layers typically associated with CNNs . The configurable nature, small real-estate, and low-power properties of FPGAs allow for computationally expensive CNNs to be moved to the node. CDL is the product of a scalable framework that offers the opportunity to stipulate the desired performance, platform specifications, and resource constraints for an application and platform-specific optimized solution
Flow
Scalability
The CDL framework is a scalable and flexible embedded deep learning solution that allows for the implementation of a wide range of convolutional neural networks on FPGAs. Considering the different sources of parallelism, minimizing the memory footprint through data quantization, and exploring the design space allows for an efficient chip specific, network specific implementation of CNNs on a FPGA.
Comprehensive Layer Support
- Concatenation Layer
- Convolution
- Pooling
- Activation
- Fully connected
- Batch normalisation
Network Compression
- Dynamic 8-bit fixed point representation
- Negligible accuracy loss
- Reduced external memory bandwidth requirements
Inference on the Node
- Moving the processing to the edge
- Package intelligent solutions into numerous edge devices
- Total solution size/footprint
- FPGA flexibility
- Embedded application power constraints
- Inference application running alongside other SOFT IP cores
- Security
Why FPGAs for inference
Core Deep Learning​
Network description
Simple model of the network that needs to be implemented
Compression
Quantise the weights and data in the network to reduce the memory footprint
Design space exploration
The platform resources and the netwok structure are used to determine yhe best design parameters
SystemVerilog
Extracted from DSE and used to generate the System Verilog
Easy Integration
CDL can fit into any FPGA design by scaling to unique customer requirements. Using search and simulation algorithms, optimal solutions are provided on a per-implementation basis. Each solution is configured specific to the network and user-specific platform requirements. The simple interface allows for fast and efficient design integration.
Object Detection Demo
Development kits supported
Microsemi Polarfire
- MPF300-EVAL-KIT-ES
- MPF300-SPLASH-KIT-ES
- EVEREST-DEV-BOARD (coming soon)
- AVMPF300TS-01 (coming soon)
Microsemi SmartFusion2
- M2S090TS-EVAL-KIT
Get in Touch
Office
1st Floor West, Midview Building
Thandanani Office Park
Invicta Road
Midrand
South Africa
E Mail
Call Us:
+27 (0)11 315 8316