CDL Final Logo #001

A deep learning platform optimized
for implementation on FPGAs

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Core Deep Learning (CDL) from ASIC Design Services is a scalable and flexible Convolutional Neural Network (CNN) solution for FPGAs. CDL accelerates a wide range of layers typically associated with CNNs . The configurable nature, small real-estate, and low-power properties of FPGAs allow for computationally expensive CNNs to be moved to the node. CDL is the product of a scalable framework that offers the opportunity to stipulate the desired performance, platform specifications, and resource constraints for an application and platform-specific optimized solution.



The CDL framework is a scalable and flexible embedded deep learning solution that allows for the implementation of a wide range of convolutional neural networks on FPGAs. Considering the different sources of parallelism, minimizing the memory footprint through data quantization, and exploring the design space allows for an efficient chip specific, network specific implementation of CNNs on a FPGA.

Comprehensive Layer Support

Network Compression

Inference on the Node

Why FPGAs for inference

Core Deep Learning​

Network description

Simple model of the network that needs to be implemented


Quantise the weights and data in the network to reduce the memory footprint

Design space exploration

The platform resources and the netwok structure are used to determine yhe best design parameters


Extracted from DSE and used to generate the System Verilog

Network description

Easy Integration

CDL can fit into any FPGA design by scaling to unique customer requirements. Using search and simulation algorithms, optimal solutions are provided on a per-implementation basis. Each solution is configured specific to the network and user-specific platform requirements. The simple interface allows for fast and efficient design integration.

Object Detection Demo

Detections #02

Development kits supported

Microchip Polarfire

Microchip SmartFusion2

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